An Efficient FPGA-based Design and Implementation of AES Algorithm

Abstract

This paper presents an FPGA based hardware design and implementation of a 128 bit AES encryption
processor. Synthesis is achieved using Verilog code implemented on the FPGA. Two different architectures are
presented, the basic iterative architecture which achieves low FPGA resources requirements, 347 slices and 10
BRAM and a maximum throughput is 1.3988Gbps. And the fully pipelined architecture of AES encryption
processor for higher speed applications. The second architecture achieved 31.4574 Gbps as maximum throughput
and using 30 Block RAM. These designs utilize the low cost and low power Spartan3E(TM) FPGA. Hardware
verification has been performed on the Spartan-3E starter board (xc3s500e-4) and the results were similar to
simulation results.